Semiconductor devices continue to be scaled to smaller sizes. Various design and/or process parameters may limit the scalability of the devices. The alignment of contact holes formed between layers in a semiconductor substrate is one area where scaling is limited due to the need for sufficient contact space on the lower layer to allow for alignment of the contact holes. Self-aligned contacts (SAC) are one approach to aggressively scale the contact space. SAC relies on lithographic patterning and etching of an oxide gap fill material to create the contact holes in the below layers. Due to the etch selectivity of the oxide gap fill material and spacer layers (e.g., nitride) the resultant contact holes may have a sloped or eroded profile. This can lead to undesired process variability and variability in the fill density of the SAC. Furthermore, the patterning of the oxide layer is not easily scalable for lithography and presents increased risk for resist island lifting defects at smaller feature sizes. Moreover, the SAC flow may require the purchase of an advanced dielectric etch tool to support the high selectivity and control requirements.